UVM

Universal Verification Methodology — the industry standard for building reusable, scalable verification environments. From sequences to VIP to design patterns.

28 posts

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Foundations

5 posts

Why Every DV Engineer Should Think Like a Software Engineer The mindset shift that makes UVM click — software principles applied to verification. Running UVM 1.2 Testbench — Quick Start Compile, elaborate, and run your first UVM testbench from scratch. IEEE UVM 1800.2-2017 LRM The official language reference manual — essential bookmark for every UVM engineer. Understanding Verification IP (VIP) What VIP is, why it exists, and how to use third-party VIP in your environment. Programming Paradigms: Three Thinking Modes Procedural, OOP, and functional thinking — and when to apply each in verification.

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Sequences

6 posts

UVM Sequences Fundamentals Sequences, sequence items, and the sequencer — explained through a software engineer's lens. Sequencer Arbitration & Control Managing concurrent sequences with priority, lock, and grab mechanisms. Virtual Sequences — The Mediator Pattern Coordinate multiple agents from a single virtual sequence using the mediator design pattern. Advanced Sequence Architectures Layered, pipelined, and reactive sequence patterns for complex stimulus generation. Getting Config in Sequences with Null Sequencer Access uvm_config_db from a sequence that runs on a null sequencer. UVM Barrier — Synchronizing Parallel Components Block multiple sequences or threads until all reach a synchronization point.

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Design Patterns

4 posts

Creational Patterns: Factory & Builder UVM factory overrides and builder patterns for flexible component construction. Structural Patterns: Adapter, Facade, Composite Wrap legacy VIP, simplify agent interfaces, and build hierarchical environments. OOP in SystemVerilog — Polymorphism Virtual methods, class handles, and runtime dispatch — the foundation of UVM extensibility. OOP in SystemVerilog — Abstract Classes Pure virtual methods and abstract base classes — how UVM enforces contracts.

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Advanced Components

4 posts

UVM Heartbeat — Detecting Hung Components Monitor components for liveness and catch hung sequences before timeout. UVM Report Catcher — Filtering Messages Intercept, modify, or suppress UVM messages without changing source code. SystemVerilog & UVM Callbacks Extend component behavior at runtime without subclassing using the callback mechanism. Cleaner Way to Kill a Fork/Join Thread Safely disable parallel threads in UVM without resource leaks or race conditions.

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Python-UVM Series

4 posts

Part 1 Introduction & Overview Why Python and UVM together — architecture overview and DPI-C bridge concept. Part 2 Building the DPI-C Bridge Step-by-step guide to implementing the C shim that connects Python to SystemVerilog. Part 3 Test Patterns & Best Practices Reusable Python test patterns — parameterized tests, fixtures, and assertion helpers. Part 4 Architecture at Scale — Python in SoC Scaling the Python-UVM bridge to full SoC verification with multiple agents.

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VIP & Protocols

3 posts

AMBA AHB 2.0 VIP in SystemVerilog/UVM Complete VIP implementation for the AHB 2.0 bus protocol with UVM agents. AMBA AHB-APB Bridge UVM Environment Full UVM verification environment for an AHB-to-APB bridge design. Learn UVM Environment with AMBA APB Hands-on walkthrough of a complete UVM environment using APB protocol as the DUT.

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Performance

2 posts

Complexity Analysis: Why Your Testbench Is Slow Big-O analysis applied to UVM testbenches — find and fix performance bottlenecks. Memory Management: Surviving Long Simulations Prevent memory leaks and OOM crashes in UVM environments running for hours.