Once SV/UVM testbench has been developed it might not be feasible to make changes in testbench blocks with RTL changes. So, to provide this extra functionality without going into original testbench and making changes, 'hooks' are provided in the testbench during initial development phase.
These 'hooks' can be used to extend functionality of blocks, error injection in existing functionality etc. Rather than implementing all types of possible error scenarios or extra features in the Driver component, special tests can be for specific features. This can be achieved through 'callbacks' mechanism provided by OOPs in SystemVerilog or UVM.
Here, I'll address SystemVerilog callbacks first using OOPs concept and then UVM callback mechanism.
These 'hooks' can be used to extend functionality of blocks, error injection in existing functionality etc. Rather than implementing all types of possible error scenarios or extra features in the Driver component, special tests can be for specific features. This can be achieved through 'callbacks' mechanism provided by OOPs in SystemVerilog or UVM.
Here, I'll address SystemVerilog callbacks first using OOPs concept and then UVM callback mechanism.
