This AMBA AHB 2.0 Verification IP is implemented in SystemVerilog with Universal Verification Methodology.
It features
- Single master - slave protocol
- All burst type transactions
- 8, 16, 32 bit data bus width and 32bit address bus
- Delaying transactions with IDLE insertion and Low READY signals
Run the tests with Python script provided with the code. The script uses QuestaSim commands to run the simulation.
I'll update this post with UVM VIP Architecture explanation and AHB SystemVerilog Assertions(SVA).
Here
Please your suggestions in comment below.
It features
- Single master - slave protocol
- All burst type transactions
- 8, 16, 32 bit data bus width and 32bit address bus
- Delaying transactions with IDLE insertion and Low READY signals
Run the tests with Python script provided with the code. The script uses QuestaSim commands to run the simulation.
I'll update this post with UVM VIP Architecture explanation and AHB SystemVerilog Assertions(SVA).
Here
Please your suggestions in comment below.
