AMBA AHB 2.0 VIP implementation in SystemVerilog, UVM.

A complete AMBA AHB 2.0 Verification IP implemented in SystemVerilog using the Universal Verification Methodology (UVM).

Features

• Single Master-Slave protocol support
• All burst types: SINGLE, INCR, WRAP4, INCR4, WRAP8, INCR8, WRAP16, INCR16
• Configurable data width: 8, 16, 32-bit
• 32-bit address bus
• Wait state insertion: IDLE cycles and HREADY low delays

Project Structure

ahb2_uvm_tb/
├── ahb_env/           # Top-level environment
├── ahb_master_agent/  # AHB master agent (driver, monitor, sequencer)
├── ahb_slave_agent/   # AHB slave agent
├── ahb_test/          # Test cases
├── reset_agent/       # Reset signal management
├── rtl/               # Reference RTL design
└── sim/               # Simulation scripts

Architecture

%%{init: {'theme': 'base', 'themeVariables': {'primaryColor': '#e0f2fe', 'primaryTextColor': '#0f172a', 'primaryBorderColor': '#0066cc', 'lineColor': '#475569', 'secondaryColor': '#f8fafc'}}}%%
flowchart TB
    subgraph TEST["ahb_test"]
        TC[Test Cases]
        SEQ[Sequences]
    end

    subgraph ENV["ahb_env"]
        subgraph MAGT["ahb_master_agent"]
            MDRV[Driver]
            MMON[Monitor]
            MSEQR[Sequencer]
        end
        
        subgraph SAGT["ahb_slave_agent"]
            SDRV[Slave Driver]
            SMON[Slave Monitor]
        end
        
        SCB[Scoreboard]
        COV[Coverage]
    end

    subgraph RAGT["reset_agent"]
        RST[Reset Driver]
    end

    DUT{{AHB DUT}}

    TC --> SEQ
    SEQ --> MSEQR
    MSEQR --> MDRV
    MDRV -->|AHB Signals| DUT
    DUT -->|AHB Signals| SDRV
    MMON -.-> SCB
    SMON -.-> SCB
    MMON -.-> COV
    RST -->|Reset| DUT

    style DUT fill:#d1fae5,stroke:#10b981,stroke-width:2px
    style SCB fill:#fef3c7,stroke:#f59e0b,stroke-width:2px

AHB Signal Interface

Signal	Width	Description
HCLK	1	Bus clock
HRESETn	1	Active-low reset
HADDR	32	Address bus
HTRANS	2	Transfer type (IDLE, BUSY, NONSEQ, SEQ)
HWRITE	1	Write enable
HSIZE	3	Transfer size
HBURST	3	Burst type
HWDATA	32	Write data
HRDATA	32	Read data
HREADY	1	Transfer complete
HRESP	2	Transfer response

Running Tests

Tests can be run using the provided Python script with QuestaSim:

cd sim/
python run_test.py --test ahb_base_test

Source Code

View on GitHub: AHB 2.0 UVM Testbench