IEEE UVM 1800.2-2017 Language Reference Manual(LRM) Specification

The IEEE 1800.2-2017 standard defines the Universal Verification Methodology (UVM) - a standardized methodology for verifying integrated circuit designs.

About IEEE 1800.2-2017

This specification provides:

• Class library reference: Complete API documentation for all UVM base classes
• Methodology guidelines: Best practices for building reusable verification components
• Factory patterns: Configuration and override mechanisms
• Phasing: Standardized simulation phases (build, connect, run, etc.)
• TLM interfaces: Transaction-level modeling ports and exports

Key Components

Component	Description
uvm_component	Base class for all hierarchical components
uvm_object	Base class for transactions and configurations
uvm_sequence	Stimulus generation mechanism
uvm_driver	Converts transactions to pin-level activity
uvm_monitor	Observes DUT interface activity
uvm_scoreboard	Checks expected vs actual results

Download

The IEEE 1800.2-2017 UVM Language Reference Manual is available for free download through the IEEE Get Program:

Download IEEE 1800.2-2017 UVM LRM

Note: This standard supersedes the Accellera UVM 1.2 release and is the official IEEE standardized version of UVM.