SystemVerilog

Language features, OOP, assertions, design patterns, and UVM integration — everything you need to write professional-grade SystemVerilog.

27 posts

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Language Core

7 posts

SystemVerilog Classes & Objects — Complete Guide Class declaration, constructors, handles, inheritance, and polymorphism from first principles. SystemVerilog Cheatsheet Quick reference for data types, operators, procedural blocks, and class syntax. OOP — Polymorphism Virtual methods and runtime dispatch — how SV handles dynamic type resolution. OOP — Abstract Classes Pure virtual methods and abstract base classes for defining verification interfaces. Gotcha: Function in Constraint — Solve-Before Trap The hidden ordering trap when calling functions inside constraint blocks. Cleaner Way to Kill a Fork/Join Thread Safely disable parallel threads without leaks using disable fork patterns. Reference — Language & Methodology Manuals Curated links to IEEE SV, UVM, and SVA standards — the definitive references.

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Assertions (SVA)

2 posts

Part 1 SVA Guide — Immediate Assertions assert, assume, and cover — the building blocks of SystemVerilog assertion-based verification. Part 2 SVA Guide — Concurrent Assertions Sequence operators, property definitions, and clock-driven assertion evaluation.

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Design Patterns

2 posts

Creational Patterns: Factory & Builder Apply factory and builder patterns to build flexible, configurable testbench components. Structural Patterns: Adapter, Facade, Composite Structural patterns that make complex verification environments easier to compose and extend.

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Sequences & UVM

5 posts

UVM Sequences Fundamentals Sequences, sequence items, and sequencer — core UVM stimulus generation mechanics. Sequencer Arbitration & Control Priority, lock, and grab — managing concurrent sequence execution on a single sequencer. Virtual Sequences — The Mediator Pattern Coordinate multi-agent stimulus from a single top-level virtual sequence. Advanced Sequence Architectures Layered, pipelined, and reactive patterns for sophisticated stimulus generation. Getting Config in Sequences — Null Sequencer Access uvm_config_db from sequences that start on a null sequencer handle.

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Python-SV Bridge

4 posts

Part 1 Introduction & Overview Driving UVM testbenches from Python via DPI-C — architecture and motivation. Part 2 Building the DPI-C Bridge The C shim layer that binds Python function calls to SystemVerilog tasks. Part 3 Test Patterns & Best Practices Reusable Python patterns for stimulus generation, coverage, and regression. Part 4 Architecture at Scale — Python in SoC Scaling Python-driven verification to a full multi-agent SoC environment.

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VIP & Testbenches

4 posts

AMBA AHB 2.0 VIP in SystemVerilog/UVM Complete AHB 2.0 VIP: agent, driver, monitor, scoreboard, and coverage. AMBA AHB-APB Bridge UVM Environment Full UVM testbench for an AHB-to-APB bridge — from spec to coverage closure. Learn UVM Environment with AMBA APB Hands-on UVM environment walkthrough using APB as the protocol under test. Verilog Pattern Printing — Interview Deep Dive Classic interview question dissected — loops, simulation, and thinking on your feet.

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Performance & Tools

3 posts

Complexity Analysis: Why Your Testbench Is Slow Apply Big-O thinking to find which part of your testbench is the real bottleneck. Memory Management: Surviving Long Simulations Identify and fix memory leaks in UVM environments running multi-hour regressions. Programming Paradigms: Three Thinking Modes Procedural, OOP, and functional — knowing which mode to use is a superpower.