Understanding Verification IP (VIP)

A Verification IP (VIP) is a reusable verification component designed to verify standard protocol interfaces. Unlike regular testbenches built around a specific RTL, VIPs are developed independently and can be integrated into any design that uses the target protocol.

Traditional Testbench Development

Given an RTL, one can design a testbench around it using SystemVerilog with UVM. The typical approach is:

• Analyze RTL top block and develop testplan
• Develop Driver/Monitor blocks for inputs and outputs
• Integrate DUV (Design Under Verification)
• Apply inputs and observe responses

VIP Development Process

VIP development runs in parallel to RTL design. Once specifications are ready, a verification engineer starts developing the VIP without waiting for RTL. This approach includes:

• Preparing Verification Plan (The Vplan)
• Develop UVCs (UVM Verification Components)
• Write Protocol Checkers (Using SVA)
• Functional Coverage

All of these are done without including RTL. Let's examine each step in detail.

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1. Preparing Verification Plan

The Verification Plan includes requirements interpreted from the design specification. It contains:

• List of all features to verify
• How to verify each feature (assertions, coverage bins, directed tests)
• Coverage tracking methodology

Documentation is typically maintained in spreadsheets or XML format. A detailed Vplan guides the development of UVCs (Agent blocks containing Sequencer, Driver, Monitor).

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2. Develop UVCs

Agent blocks are called UVCs because they contain a Sequencer-Driver-Monitor triad that is interface-specific.

The key advantage: For a particular interface, you can take a previously developed UVC (e.g., APB Master UVC) and integrate it into different architectures containing that interface (e.g., AHB-APB Bridge). This makes UVCs reusable components across multiple verification environments.

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3. Write Protocol Checkers

Protocol checks are written using SystemVerilog Assertions (SVA). These can be:

• Immediate Assertions: Embedded in protocol-specific components (e.g., Monitor)
• Concurrent Assertions: Written in the interface module for continuous checking

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4. Functional Coverage

Functional coverage is implemented in a Coverage Module (extended from uvm_subscriber). Since protocol checks are handled by assertions, traditional scoreboarding is often unnecessary in VIPs.

VIPs are designed with 100% functional coverage as the goal. Features listed in the Vplan are covered using:

• Functional coverage (covergroups, coverpoints, crosses)
• Assertion coverage