Verification IP
One develops testbench for functional verification of IP (RTL Core). Given an RTL, one can design testbench around it using SystemVerilog with OVM/UVM. In the process, approach followed is,
Take a look at RTL top block, develop testplan.
Develop Driver/Monitor blocks for Inputs and Outputs
Integrate DUV
Apply Inputs and observe Response
But developing testbench architecture runs in parallel to RTL design. Meaning, once specifications are ready a verification engineer starts developing testbench without waiting for an RTL. Considering this fact, development flow for VIP is slightly different that development of regular testbench. VIP development process includes,
Preparing Verification Plan (The Vplan)
Develop UVCs
Write Protocol Checkers (Using SVA)
Functional Coverage
And all of these are done without including RTL. Lets take a look at each step in detail.
Preparing Verification Plan
Verification Plan includes requirements interpreted from design specification. It contains a list of all features, how to verify those features (use assertions/bins/test etc). For documentation spreadsheets or XML is used. In conclusion, Vplan contains briefings about all features interpreted from specification and a way to track (assertion/bins etc) coverage of all features. A detailed verification plan helps develop UVCs (Agent block containing Sequencer, Driver, Monitor).
Develop UVCs
Generally Agent blocks are called UVCs because they contains Sequencer-Driver & Monitor pair which are interface specific. And for a particular interface you can take previously developed UVC (Say APB Master UVC) and integrate it into different architecture containing APB interface as input/output of DUV (Say AHB - APB Bridge DUV). That way UVCs are reusable component in a UVM Verification Environment.
Write Protocol Checkers
Protocol checks are usually written with SystemVerilog Assertions (SVA). These protocol checks can be embedded into protocol specific components (e.g. Monitor), these are immediate checks (Immediate Assertions). Also protocol checks can be written into interface module, they are called concurrent assertions.
Functional Coverage
Functional coverage can be written in Scoreboard/ Coverage Module (extended from uvm_subscriber). As all checks are done using assertions, no other checking methods are required in an VIP, so no Scoreboarding is needed. That's why we make use of Coverage module which is extended from uvm_subscriber class. VIPs are created keeping in mind 100% functional coverage. Functions listed in V-Plan can be covered using functional coverage or assertion coverage.
