Resources
A curated collection of official resources for VLSI Design and Verification engineers. Conference papers, specifications, and vendor documentation.
Conference Papers & Publications
DVCon Papers
Design and Verification Conference papers on UVM, SystemVerilog, formal verification, and methodology.
DAC Papers
Design Automation Conference - the premier EDA conference covering design, verification, and tools.
SNUG Papers
Synopsys Users Group conference papers on synthesis, simulation, and verification methodologies.
Standards & Specifications
IEEE Standards
Official IEEE standards for SystemVerilog (1800), UVM (1800.2), VHDL (1076), and PSL (1850).
PCIe Specifications
PCI Express base specifications and related protocol documents from PCI-SIG.
Computer Architecture
ETH Zurich - Computer Architecture
Prof. Onur Mutlu's comprehensive computer architecture course materials and lectures.
RISC-V International
Official RISC-V ISA specifications and technical documentation.
arXiv Papers
Open-access research papers on processor architecture, RISC-V verification, and microarchitecture.
AI & LLMs for Hardware Design
Research Papers
Academic research on using Large Language Models for RTL generation and verification.
Prompt Engineering
Official documentation on prompt engineering from AI providers.
Open Source Tools
Verilator
Fast, open-source Verilog/SystemVerilog simulator and lint tool.
cocotb
Python-based testbench framework for verifying VHDL and Verilog RTL.
This page is regularly updated with new resources. Have a suggestion? Leave a comment below!