Running UVM 1.2 Testbench - Quick Start

Most simulators ship with a UVM library built in (QuestaSim's -uvm flag, VCS's -ntb_opts uvm-1.2, etc.) — but knowing how to compile against the Accellera reference release manually is what unblocks you when something goes wrong. This guide walks the QuestaSim flow for the Accellera UVM 1.2 release, covers the runtime plus-args that actually matter, and ends with the most common compile errors and what they're really telling you.

UVM simulation lifecycle

flowchart LR
  A[Compile
vlog/vlogan] --> B[Elaborate
build phase]
  B --> C[connect_phase]
  C --> D[end_of_elab]
  D --> E[start_of_simulation]
  E --> F[run_phase
raise_objection]
  F --> G[Sequences run
Driver/Monitor active]
  G --> H[drop_objection]
  H --> I[extract / check / report]
  I --> J[Report summary
UVM_INFO/WARNING/ERROR]

Every phase is overridable. Most user code lives in build_phase, connect_phase, and run_phase; the others handle wrap-up.

Step 1 — Get the UVM 1.2 source

Download the UVM 1.2 release from Accellera. Extract anywhere; the package file you'll need is at:

uvm-1.2/src/uvm_pkg.sv

Note: UVM 1.2 was superseded by IEEE 1800.2 in 2017 (and revised in 2020). For new projects use the IEEE release. The 1.2 flow shown here is essentially identical for 1800.2 — just point at the newer source tree. See the IEEE 1800.2 LRM guide for what changed.

Step 2 — Compile + run with QuestaSim

# Create work library
vlib myWork
vmap work myWork

# Compile (UVM lib + your TB) using a file list
vlog -work myWork -f tb.f +define+UVM_NO_DPI

# Run, picking the test by plus-arg
vsim -c work.tb_top \
     +UVM_TESTNAME=my_basic_test \
     +UVM_VERBOSITY=UVM_MEDIUM \
     -do "run -all; quit -f"

The file list tb.f

# UVM source
+incdir+uvm-1.2/src
uvm-1.2/src/uvm_pkg.sv

# Your testbench
+incdir+./tb
./tb/tb_pkg.sv
./tb/tb_top.sv

# DUT
./rtl/dut.v

Step 3 — The flags that actually matter

Flag	Where	Effect
+incdir+<path>	Compile	Include directories searched by `include directives
+define+UVM_NO_DPI	Compile	Disable DPI; required when DPI is unsupported or disabled. Some advanced features (regmodel backdoor) won't work.
+define+UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR	Compile	Allow uvm_object subclasses without explicit ctor (lenient compile)
+UVM_TESTNAME=<test>	Runtime	Selects the test class — required for any UVM run
+UVM_VERBOSITY=UVM_LOW / UVM_MEDIUM / UVM_HIGH / UVM_FULL / UVM_DEBUG	Runtime	Controls which uvm_info messages print
+UVM_TIMEOUT=<ns>,YES	Runtime	Forces a timeout; use to catch hung sequences
+uvm_set_config_int=<path>,<name>,<value>	Runtime	Override config DB entries from the command line
+uvm_set_verbosity=<path>,<id>,<verb>,<phase>	Runtime	Adjust verbosity for a specific component

Makefile-driven flow (recommended)

Putting the commands in a Makefile makes regressions and CI tractable.

UVM_HOME ?= ./uvm-1.2/src
TEST     ?= my_basic_test
VERB     ?= UVM_MEDIUM
SEED     ?= random

.PHONY: comp sim clean

comp:
\tvlib work
\tvlog -f tb.f +define+UVM_NO_DPI +incdir+$(UVM_HOME)

sim: comp
\tvsim -c work.tb_top \
\t  +UVM_TESTNAME=$(TEST) \
\t  +UVM_VERBOSITY=$(VERB) \
\t  -sv_seed $(SEED) \
\t  -do "run -all; quit -f"

clean:
\trm -rf work transcript vsim.wlf

Then runs reduce to:

make sim TEST=my_random_test VERB=UVM_HIGH SEED=42

Common compile/run errors

Symptom	What it means	Fix
Cannot find package uvm_pkg	+incdir doesn't include UVM source path	Add +incdir+$(UVM_HOME) and ensure uvm_pkg.sv is in the file list
Failed to find a default sequence ...	+UVM_TESTNAME not provided or test class isn't registered	Pass +UVM_TESTNAME=... on the runtime command; verify `uvm_component_utils macro is on the test class
UVM_ERROR ... Factory: cannot create object of type X	Class isn't registered with the factory	Add `uvm_component_utils(X) or `uvm_object_utils(X)
UVM_FATAL ... Objection raised in run_phase but never dropped	Sequence completed but objection still raised	Pair every raise_objection(this) with drop_objection(this) in the same scope
Sim exits at time 0 with no work done	No test instantiated uvm_test_top	Ensure run_test() is called from the SV testbench top module
DPI link errors	UVM was compiled with DPI but simulator can't link	Add +define+UVM_NO_DPI at compile time, or build the UVM C library and link with -sv_lib

What you've got working

Compile, run, control verbosity, override config from the command line, get a deterministic seed for replays. That's the operational baseline. From here, the real UVM learning is in what you put inside the testbench: sequences, register models, scoreboards, virtual interfaces. The reference for that is the IEEE 1800.2 LRM — see the navigation guide for how to read it efficiently.