Learn SystemVerilog UVM Environment with AMBA APB Protocol/APB VIP

In a SystemVerilog/UVM testbench, multiple components work together to verify the DUT. This post explains each component using an AMBA APB protocol example.

Testbench Architecture

%%{init: {'theme': 'base', 'themeVariables': {'primaryColor': '#dbeafe', 'primaryTextColor': '#1e293b', 'primaryBorderColor': '#3b82f6', 'lineColor': '#64748b', 'secondaryColor': '#f1f5f9', 'tertiaryColor': '#ffffff'}}}%%
flowchart TB
    subgraph TEST["Test"]
        subgraph ENV["Environment"]
            subgraph MASTER["Master Agent"]
                MS([seqr]) --> MD[driver]
                MM[monitor]
            end
            subgraph SLAVE["Slave Agent"]
                SS([seqr]) --> SD[driver]
                SM[monitor]
            end
            subgraph RST["Reset Agent"]
                RS([seqr]) --> RD[driver]
            end
            COV[coverage]
        end
    end

    MM & SM --> COV
    MD & SD <==> IF{{apb_if}}
    RD -.->|PRESETn| IF

    classDef agent fill:#dbeafe,stroke:#3b82f6
    classDef interface fill:#d1fae5,stroke:#10b981
    classDef seqr fill:#fef3c7,stroke:#f59e0b
    class MASTER,SLAVE,RST agent
    class IF interface
    class MS,SS,RS seqr

UVM Component Hierarchy

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flowchart LR
    subgraph Components
        T[Test] --> E[Env]
        E --> A1[Agent]
        E --> A2[Agent]
        E --> S[Scoreboard]
        A1 --> D[Driver]
        A1 --> M[Monitor]
        A1 --> Q([Sequencer])
    end

    classDef default fill:#dbeafe,stroke:#3b82f6
    classDef seqr fill:#fef3c7,stroke:#f59e0b
    class Q seqr

Component Descriptions

Component	Role
Test	Creates environment, starts sequences
Environment	Container for agents and scoreboard
Agent	Reusable verification component (driver + monitor + sequencer)
Driver	Converts transactions to pin-level signals
Monitor	Observes interface, creates transactions
Sequencer	Controls transaction flow to driver
Coverage	Collects functional coverage

APB Signal Flow

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flowchart LR
    M[Master] -->|PADDR, PWDATA| BUS{{APB Bus}}
    M -->|PSEL, PENABLE| BUS
    BUS -->|PRDATA| M
    BUS -->|PREADY, PSLVERR| M
    BUS <--> S[Slave]

    classDef bus fill:#d1fae5,stroke:#10b981
    class BUS bus

APB Write Transaction

{"signal": [
  {"name": "PCLK", "wave": "p......."},
  {"name": "PSEL", "wave": "0.1...0."},
  {"name": "PENABLE", "wave": "0..1..0."},
  {"name": "PWRITE", "wave": "0.1...0."},
  {"name": "PADDR", "wave": "x.3...x.", "data": ["ADDR"]},
  {"name": "PWDATA", "wave": "x.4...x.", "data": ["DATA"]},
  {"name": "PREADY", "wave": "0....10."},
  {}
], "config": {"hscale": 1.5}}

Topics Covered

• AMBA APB Protocol basics
• UVM testbench architecture
• Top module and Interface
• APB Transaction class
• Driver, Sequencer and Sequences
• Monitor and Agent
• Environment and Test

Resources

APB Specification: ARM AMBA Specifications

Source Code: APB2 UVM Testbench on GitHub