In a SystemVerilog/UVM testbench environment, many components are included such as,
1) Driver - Sequencer to drive transactions to the DUV.
2) Monitor - To collect interface data and send for Functional Coverage.
3) Agent - UVC to group above two so as to make them easily reusable.
4) Scoreboard/Checker - Checks data integrity.
5) Coverage Monitor - Collects transactions from Monitor component to sample coverage.
5) Environment - Group of above all components.
6) Test - Test created the Environment as per test configurations.
7) Others - These includes Assertion module, Interface, Top module etc.
Here, all the above topics are explained with AMBA APB protocol example. To get detailed information on APB, please refer the ARM APB specification HERE
Also code for APB2 UVM testbench is available on GitHub HERE
1) Driver - Sequencer to drive transactions to the DUV.
2) Monitor - To collect interface data and send for Functional Coverage.
3) Agent - UVC to group above two so as to make them easily reusable.
4) Scoreboard/Checker - Checks data integrity.
5) Coverage Monitor - Collects transactions from Monitor component to sample coverage.
5) Environment - Group of above all components.
6) Test - Test created the Environment as per test configurations.
7) Others - These includes Assertion module, Interface, Top module etc.
Here, all the above topics are explained with AMBA APB protocol example. To get detailed information on APB, please refer the ARM APB specification HERE
Also code for APB2 UVM testbench is available on GitHub HERE
- AMBA APB Protocol
- UVM testbench overview
- Top and Interface module
- APB Transaction
- Driver/Sequencer and Sequence
- Monitor and Agent
- Env and Test
