Verilog RTL for D Flip Flop with Asynchronous Active High Reset

//////////////////////////////////
// Dff with Asynchronous Reset
// Inputs: Clock, Reset, Din
// Outputs: Q, Qbar
// Design By:
// Date: 12 May 2015
//////////////////////////////////

module dff(clk, rst, d, q, qbar);

   input clk, rst, d;
   output q, qbar;
   reg    q;

   assign qbar = ~q;

   always@(posedge clk or posedge rst) begin
      if(rst) q <= 1'b0;
      else q <= d;
   end

endmodule // dff