Use Verilog Task in RTL, 4:1 Mux

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

module mux_t(input [3:0]in, input[1:0] sel, output reg y); task t_mux; input [3:0] i; input [1:0] s; output reg y; begin case(s) 2'b00: y = in[0]; 2'b01: y = in[1]; 2'b10: y = in[2]; 2'b11: y = in[3]; endcase end endtask always@(in,sel) begin t_mux(in, sel, y); end endmodule

Code highlight hilite.me