Verilog Tasks in RTL - 4:1 Mux Example

Verilog tasks can be used in synthesizable RTL code to encapsulate reusable logic. This example demonstrates a 4:1 multiplexer implemented using a task.

About Verilog Tasks

Tasks in Verilog are similar to functions but can:

• Have multiple outputs
• Contain timing controls (delays, waits)
• Call other tasks and functions

Note: For synthesizable RTL, tasks must be combinational (no timing controls) and called from within an always block.

4:1 Mux Using Task

module mux_t(
  input  [3:0] in,
  input  [1:0] sel,
  output reg   y
);

  // Task definition for 4:1 mux
  task t_mux;
    input [3:0] i;
    input [1:0] s;
    output reg  y;
  begin
    case(s)
      2'b00: y = i[0];
      2'b01: y = i[1];
      2'b10: y = i[2];
      2'b11: y = i[3];
    endcase
  end
  endtask

  // Call task in combinational always block
  always @(in, sel) begin
    t_mux(in, sel, y);
  end

endmodule

Port Description

Port	Direction	Width	Description
in	input	4	Data inputs [3:0]
sel	input	2	Select lines [1:0]
y	output	1	Mux output

Selection Logic

sel	Output
00	in[0]
01	in[1]
10	in[2]
11	in[3]