HDL Tools - Simulators & Synthesis

A curated list of free and accessible tools for Verilog, VHDL, SystemVerilog, and UVM development.

Online Simulators

EDA Playground

edaplayground.com is a web-based simulation environment accessible from anywhere. No installation required.

Supported Languages:

• SystemVerilog / Verilog
• UVM / OVM
• VHDL
• C++ / SystemC
• Python, Perl, Csh
• Specman e

Desktop Simulators

ModelSim (Mentor Graphics)

Free student edition available from Mentor Graphics.

Note: Randomization features are not supported in ModelSim. For constrained random verification, you'll need QuestaSim.

Icarus Verilog

Icarus Verilog is an open-source Verilog compiler supporting IEEE Std 1364-2005. Excellent choice for Linux users.

Features:

• Nearly complete IEEE 1364-2005 support
• Cross-platform (Linux, macOS, Windows)
• Active open-source development

Tool Comparison

Tool	Type	Languages	Randomization
EDA Playground	Online	SV, Verilog, UVM, VHDL, SystemC	Yes
ModelSim SE	Desktop	SV, Verilog, VHDL	No
QuestaSim	Desktop	SV, Verilog, UVM, VHDL	Yes
Icarus Verilog	Desktop	Verilog	No