HDL Tools - Simulators & Synthesis

The HDL tooling landscape has shifted dramatically in the last decade. Open-source simulators and synthesizers are now legitimate options for serious work — Verilator routinely outpaces commercial simulators for cycle-accurate modeling, and CocoTB has changed how Python-fluent engineers write testbenches. This is a 2026-current map of what's actually used, free and commercial, with notes on when each tool fits.

Decision tree — which tool, when

flowchart TD
  A[What are you doing?] --> B{Quick experiment
or learning?}
  B -->|Yes| C[EDA Playground
browser, no install]
  B -->|No| D{Commercial license
available?}
  D -->|Yes| E{What language?}
  E -->|SV / UVM| F[QuestaSim / VCS / Xcelium]
  E -->|VHDL| G[QuestaSim / Riviera-PRO]
  D -->|No| H{Need fast
cycle-accurate sim?}
  H -->|Yes| I[Verilator
compiles to C++]
  H -->|No| J{Language?}
  J -->|Verilog| K[Icarus Verilog]
  J -->|VHDL| L[GHDL]
  J -->|Python TB| M[CocoTB +
Icarus / Verilator]

Online & In-Browser

EDA Playground

edaplayground.com remains the fastest way to share a runnable example or test an idea. Free tier gives you ModelSim, Icarus, and Verilator; paid tier unlocks QuestaSim, VCS, and Xcelium.

Supported languages: SystemVerilog / Verilog / UVM / VHDL / SystemC / C++ / Python.

Open-Source Simulators

Verilator (the heavyweight)

Verilator compiles synthesizable Verilog/SystemVerilog into C++ that runs as a native binary. It's not event-driven — it's cycle-accurate — which makes it 10–100× faster than commercial event simulators for the kinds of designs that fit. Used in production by Google, Western Digital, Tenstorrent, and the open-source CPU community.

• Strengths: Speed, free, modern SystemVerilog subset
• Limitations: No 4-state by default (X/Z), limited force/release, no native UVM
• Best for: CPU/RISC-V models, large RTL where speed matters, CocoTB or C++ testbenches

Icarus Verilog

Icarus is a classic event-driven Verilog simulator. Mature, cross-platform, IEEE 1364-2005 nearly complete. SystemVerilog support has improved but is still partial.

GHDL (VHDL)

GHDL is the de-facto open-source VHDL simulator. Supports VHDL-2008 well, integrates with GTKWave, and works with CocoTB.

CocoTB (Python testbenches)

CocoTB isn't a simulator — it's a coroutine-based testbench framework that drives any of the above (Icarus, Verilator, GHDL, plus commercial sims via VPI/VHPI). For Python-fluent teams, it's the highest-productivity testbench environment outside UVM.

Commercial Simulators

Tool	Vendor	Languages	UVM	Notes
QuestaSim	Siemens EDA	SV, VHDL, Verilog, SC	Yes	Most common in DV teams; strong debugger; Visualizer GUI
VCS	Synopsys	SV, VHDL, Verilog, SC	Yes	Strong constrained random; Verdi for debug
Xcelium	Cadence	SV, VHDL, Verilog, SC, e	Yes	Fastest constrained random in many benchmarks; SimVision/Indago debug
Riviera-PRO	Aldec	SV, VHDL, Verilog	Yes	Good price/performance for academia and small teams
ModelSim SE (legacy)	Siemens EDA	SV (limited), VHDL, Verilog	Limited	No constrained random; superseded by QuestaSim

Synthesis Tools

Open-source: Yosys

Yosys is the dominant open-source synthesis flow. Supports Verilog (and SystemVerilog via the yosys-slang frontend), targets FPGAs (iCE40, ECP5, Xilinx 7-series via nextpnr) and produces gate-level netlists for ASIC flows. Widely used for RISC-V and open-silicon projects.

FPGA vendor flows

• AMD/Xilinx Vivado — for 7-series, UltraScale, Versal. Free WebPACK edition for smaller parts.
• Intel Quartus Prime — Lite edition free for Cyclone, MAX 10. Pro for Stratix/Agilex.
• Lattice Diamond / Radiant — for ECP5, iCE40, Nexus. Limited free editions.

ASIC flows (commercial)

• Synopsys Design Compiler / Fusion Compiler — the dominant ASIC synthesis flow
• Cadence Genus / Innovus — synthesis + place-and-route
• Siemens Catapult HLS — high-level synthesis from C++/SystemC

Choosing for your situation

Situation	Pick
Learning Verilog/SV at home	Icarus + GTKWave, or EDA Playground
Constrained random / UVM, no budget	EDA Playground (free tier supports Verilator + a Python-UVM library)
Open-source CPU project	Verilator + CocoTB
Industry DV role	Whatever your team uses (typically QuestaSim, VCS, or Xcelium)
FPGA prototyping with vendor flow	Vivado / Quartus / Diamond depending on silicon
FPGA prototyping with open flow	Yosys + nextpnr

Bottom line: The free-tools gap with commercial has narrowed enormously. If you're learning at home, you can run real verification flows end-to-end without paying anyone. If you're at work, you'll use whatever the team licenses — but knowing the open-source alternatives is increasingly useful for personal projects, RTL bring-up, and CI infrastructure.