Free tools for Verilog/VHDL/SV UVM language are available from following resources,
Mentor Graphics ModelSim Simulator Source
Note: Randomization feature is not supported in any ModelSim versions. For that you will need QuestaSim simulator,
Or!
www.edaplayground.com is a great web based simulator which you can access free from anywhere, it supports SystemVerilog, Verilog, UVM/OVM, Specman e, Python, C++/SystemC, Perl, and Csh.
Another good tool for Verilog HDL language is Icarus Verilog which supports nearly complete implementation for IEEE Std 1364-2005. And it is great tool to use Verilog HDL simulator on Linux OS. Download current Icarus Verilog from FTP directory <ftp://icarus.com/pub/eda/verilog/v0.9/>.
Mentor Graphics ModelSim Simulator Source
Note: Randomization feature is not supported in any ModelSim versions. For that you will need QuestaSim simulator,
Or!
www.edaplayground.com is a great web based simulator which you can access free from anywhere, it supports SystemVerilog, Verilog, UVM/OVM, Specman e, Python, C++/SystemC, Perl, and Csh.
Another good tool for Verilog HDL language is Icarus Verilog which supports nearly complete implementation for IEEE Std 1364-2005. And it is great tool to use Verilog HDL simulator on Linux OS. Download current Icarus Verilog from FTP directory <ftp://icarus.com/pub/eda/verilog/v0.9/>.
