2. STA Fundamentals - Setup & Hold with Clock Skew

Building on STA Fundamentals, this post covers how clock skew affects setup and hold timing constraints.

What is Clock Skew?

Clock skew is the difference in clock arrival times at two flip-flops due to variations in clock distribution paths.

flowchart TD
    CLK["Clock Source"] --> B1["Buffer"]
    B1 --> B2["Buffer"]
    B1 --> B3["Buffer"]
    B2 --> B4["Buffer"]
    B3 --> B5["Buffer"]
    B4 --> FF1["FF1\n(Launch)"]
    B5 --> FF2["FF2\n(Capture)"]
    
    style CLK fill:#d1fae5,stroke:#10b981
    style FF1 fill:#dbeafe,stroke:#3b82f6
    style FF2 fill:#dbeafe,stroke:#3b82f6
    style B1 fill:#f3f4f6,stroke:#9ca3af
    style B2 fill:#f3f4f6,stroke:#9ca3af
    style B3 fill:#f3f4f6,stroke:#9ca3af
    style B4 fill:#f3f4f6,stroke:#9ca3af
    style B5 fill:#f3f4f6,stroke:#9ca3af

Clock Skew = T_capture - T_launch

Where:

• T_launch = Clock arrival time at launch FF (FF1)
• T_capture = Clock arrival time at capture FF (FF2)

Positive vs Negative Skew

Skew Type	Condition	Effect on Setup	Effect on Hold
Positive	Tcapture > Tlaunch	Helps (more time)	Hurts (less margin)
Negative	Tcapture < Tlaunch	Hurts (less time)	Helps (more margin)
Zero	Tcapture = Tlaunch	No effect	No effect

Timing with Clock Skew

flowchart LR
    subgraph CLK_PATH["Clock Paths"]
        direction TB
        SRC(["CLK"]) --> |"T_launch"| FF1
        SRC --> |"T_capture"| FF2
    end
    
    subgraph DATA_PATH["Data Path"]
        FF1["FF1"] -->|"Tc2q + Tcomb"| FF2["FF2"]
    end
    
    style FF1 fill:#dbeafe,stroke:#3b82f6
    style FF2 fill:#dbeafe,stroke:#3b82f6
    style SRC fill:#d1fae5,stroke:#10b981

Setup Time with Skew

Data launched from FF1 must arrive at FF2 before the setup time window of the next clock edge.

{ "signal": [
  { "name": "CLK@FF1", "wave": "p.....|p.....", "node": ".a" },
  { "name": "CLK@FF2", "wave": "0.p...|.p....", "node": "..b....c" },
  { "name": "FF1.Q", "wave": "x..3..|......", "data": ["D"] },
  { "name": "FF2.D", "wave": "x....4|......", "data": ["D"] },
  { "name": "", "wave": "" },
  { "name": "Skew", "wave": "x.=...|......", "data": ["+skew"] }
], "edge": ["a->b +skew", "b<->c Tclk"], "head": { "text": "Positive Skew - Setup Analysis" }, "config": { "hscale": 1.5 } }

Setup Constraint Equation

T_clk + T_skew ≥ T_c2q + T_comb + T_setup

Rearranging:

T_clk ≥ T_c2q + T_comb + T_setup - T_skew

Skew	Effect on Setup	Explanation
Positive (+)	Relaxes constraint	Capture clock arrives later, giving data more time
Negative (-)	Tightens constraint	Capture clock arrives earlier, reducing available time

Hold Time with Skew

Data must not change too quickly after the clock edge. New data from FF1 must not overwrite the current capture.

{ "signal": [
  { "name": "CLK@FF1", "wave": "p.....|p.....", "node": ".a....d" },
  { "name": "CLK@FF2", "wave": "0.p...|.p....", "node": "..b" },
  { "name": "FF1.Q (old)", "wave": "3.....|......", "data": ["D0"] },
  { "name": "FF1.Q (new)", "wave": "x.....3|.....", "data": ["D1"], "node": "......e" },
  { "name": "Hold Window", "wave": "0.1.0.|......", "node": "..f.g" }
], "edge": ["a->b +skew", "f<->g Thold", "d->e Tc2q"], "head": { "text": "Hold Time Analysis" }, "config": { "hscale": 1.5 } }

Hold Constraint Equation

T_c2q + T_comb ≥ T_hold + T_skew

Rearranging:

T_c2q + T_comb - T_skew ≥ T_hold

Skew	Effect on Hold	Explanation
Positive (+)	Tightens constraint	Capture clock delayed, new data may arrive during hold window
Negative (-)	Relaxes constraint	Capture clock earlier, more margin before new data arrives

Setup vs Hold: Skew Trade-off

flowchart LR
    subgraph POSITIVE["Positive Skew"]
        PS_SETUP["Setup: ✓ Helps"]
        PS_HOLD["Hold: ✗ Hurts"]
    end
    
    subgraph NEGATIVE["Negative Skew"]
        NS_SETUP["Setup: ✗ Hurts"]
        NS_HOLD["Hold: ✓ Helps"]
    end
    
    style PS_SETUP fill:#d1fae5,stroke:#10b981
    style PS_HOLD fill:#fee2e2,stroke:#ef4444
    style NS_SETUP fill:#fee2e2,stroke:#ef4444
    style NS_HOLD fill:#d1fae5,stroke:#10b981

Key insight: You cannot optimize for both setup and hold using skew alone. Clock Tree Synthesis (CTS) aims for minimal, balanced skew.

Example Calculation

Given:

• T_c2q = 0.3 ns
• T_comb = 2.0 ns
• T_setup = 0.2 ns
• T_hold = 0.1 ns
• T_skew = +0.5 ns (positive)

// Setup Analysis
Tclk_min = Tc2q + Tcomb + Tsetup - Tskew
         = 0.3 + 2.0 + 0.2 - 0.5
         = 2.0 ns
Fmax = 500 MHz  // Better than without skew!

// Hold Analysis  
Hold_margin = Tc2q + Tcomb - Tskew - Thold
            = 0.3 + 2.0 - 0.5 - 0.1
            = 1.7 ns  // Positive = OK

// With negative skew (-0.5 ns):
Tclk_min = 0.3 + 2.0 + 0.2 - (-0.5) = 3.0 ns  // Worse!
Hold_margin = 0.3 + 2.0 - (-0.5) - 0.1 = 2.7 ns  // Better!

Slack Equations Summary

Constraint	Slack Formula	Requirement
Setup	Tclk + Tskew - Tc2q - Tcomb - Tsetup	≥ 0
Hold	Tc2q + Tcomb - Tskew - Thold	≥ 0

Clock Uncertainty

In real designs, additional factors affect timing:

Factor	Description	Affects
Jitter	Cycle-to-cycle clock variation	Setup
OCV	On-Chip Variation (process/voltage/temp)	Both
Skew	Spatial clock arrival difference	Both

Clock Uncertainty = Jitter + Skew + OCV margin

Fixing Timing Violations

Setup Violations

• Reduce combinational delay (faster cells, logic optimization)
• Pipeline the path (add registers)
• Increase clock period (reduce frequency)
• Useful skew (intentionally delay capture clock)

Hold Violations

• Add delay buffers in data path
• Use slower cells
• Cannot be fixed by changing clock frequency!

flowchart LR
    FF1["FF1"] --> BUF1["Delay\nBuffer"] --> BUF2["Delay\nBuffer"] --> COMB["Comb"] --> FF2["FF2"]
    
    style FF1 fill:#dbeafe,stroke:#3b82f6
    style FF2 fill:#dbeafe,stroke:#3b82f6
    style BUF1 fill:#fef3c7,stroke:#f59e0b
    style BUF2 fill:#fef3c7,stroke:#f59e0b
    style COMB fill:#f3f4f6,stroke:#9ca3af

Key Takeaways

• Clock skew = T_capture - T_launch
• Positive skew helps setup, hurts hold
• Negative skew hurts setup, helps hold
• Setup violations can be fixed by reducing frequency
• Hold violations are frequency-independent (more critical!)
• CTS aims for balanced, minimal skew across the design

STA Commands (Synopsys PrimeTime)

# Report setup timing
report_timing -delay_type max -path_type full

# Report hold timing  
report_timing -delay_type min -path_type full

# Set clock uncertainty
set_clock_uncertainty -setup 0.1 [get_clocks clk]
set_clock_uncertainty -hold 0.05 [get_clocks clk]

# Report clock skew
report_clock_timing -type skew