1. STA Fundamentals - Setup Time Constraint

Static Timing Analysis (STA) verifies that digital circuits meet timing requirements without simulating actual data. This post covers setup time constraints, the foundation of STA.

What is Static Timing Analysis?

STA analyzes timing paths in a design to ensure:

• Setup time is met (data arrives early enough)
• Hold time is met (data stays stable long enough)
• Clock frequency targets are achievable

Unlike simulation, STA checks all paths exhaustively using delay models, making it faster and more complete.

Basic Timing Path

A register-to-register timing path consists of:

flowchart LR
    subgraph Launch["Launch FF"]
        FF1["FF1\n(Launch)"]
    end
    subgraph Path["Data Path"]
        COMB["Combinational\nLogic"]
    end
    subgraph Capture["Capture FF"]
        FF2["FF2\n(Capture)"]
    end
    
    CLK(["CLK"]) --> FF1
    CLK --> FF2
    FF1 -->|"Tc2q"| COMB
    COMB -->|"Tcomb"| FF2
    
    style FF1 fill:#dbeafe,stroke:#3b82f6
    style FF2 fill:#dbeafe,stroke:#3b82f6
    style COMB fill:#fef3c7,stroke:#f59e0b
    style CLK fill:#d1fae5,stroke:#10b981

Key Timing Parameters

Parameter	Symbol	Description
Clock-to-Q Delay	Tc2q	Time for data to appear at FF output after clock edge
Combinational Delay	Tcomb	Propagation delay through logic gates
Setup Time	Tsetup	Time data must be stable before clock edge
Hold Time	Thold	Time data must be stable after clock edge
Clock Period	Tclk	Time between consecutive clock edges

Setup Time Constraint

For data to be captured correctly, it must arrive at FF2 and be stable before the setup time window:

sequenceDiagram
    participant CLK as Clock
    participant FF1 as FF1 (Launch)
    participant D as Data Path
    participant FF2 as FF2 (Capture)
    
    Note over CLK: Edge 1 (Launch)
    CLK->>FF1: Clock edge
    FF1->>D: Data launches (Tc2q)
    D->>FF2: Data propagates (Tcomb)
    Note over FF2: Data must arrive here
    Note over CLK: Edge 2 (Capture)
    Note over FF2: Setup window
    CLK->>FF2: Clock edge captures

Setup Time Equation

Data must arrive before the setup time requirement of the capture flip-flop:

T_clk ≥ T_c2q + T_comb + T_setup

Rearranging for maximum frequency:

F_max = 1 / (T_c2q + T_comb + T_setup)

Timing Diagram

{ "signal": [
  { "name": "CLK", "wave": "p.....|p.....", "period": 1 },
  { "name": "FF1.Q", "wave": "x.3...|.....", "data": ["D1"], "node": "..a" },
  { "name": "Comb Out", "wave": "x...4.|.....", "data": ["D1'"], "node": "....b" },
  { "name": "FF2.D", "wave": "x...4.|.....", "data": ["D1'"], "node": "....c" },
  { "name": "", "wave": "" },
  { "name": "Setup Window", "wave": "0...1.|0....", "node": "....d.e" }
], "edge": ["a->b Tcomb", "d<->e Tsetup"], "head": { "text": "Setup Time Analysis" }, "config": { "hscale": 1.5 } }

Example Calculation

Given:

• T_c2q = 0.3 ns (clock-to-Q delay)
• T_comb = 2.5 ns (combinational delay)
• T_setup = 0.2 ns (setup time)

// Minimum clock period
Tclk_min = Tc2q + Tcomb + Tsetup
         = 0.3 + 2.5 + 0.2
         = 3.0 ns

// Maximum frequency
Fmax = 1 / 3.0 ns = 333 MHz

Setup Slack

Slack indicates timing margin. Positive slack means timing is met.

Setup Slack = T_clk - (T_c2q + T_comb + T_setup)

Slack	Status	Action
Positive	Timing Met	Design passes, margin available
Zero	Timing Met	No margin, risky
Negative	Timing Violated	Must fix: reduce logic, pipeline, faster cells

Critical Path

The critical path is the longest timing path that determines maximum frequency. STA tools report this path for optimization.

flowchart LR
    FF1["FF1"] --> A["AND"] --> B["OR"] --> C["MUX"] --> D["ADD"] --> FF2["FF2"]
    
    style FF1 fill:#dbeafe,stroke:#3b82f6
    style FF2 fill:#dbeafe,stroke:#3b82f6
    style A fill:#fee2e2,stroke:#ef4444
    style B fill:#fee2e2,stroke:#ef4444
    style C fill:#fee2e2,stroke:#ef4444
    style D fill:#fee2e2,stroke:#ef4444

Launch vs Capture

Term	Flip-Flop	Role
Launch	FF1 (Source)	Sends data on clock edge 1
Capture	FF2 (Destination)	Receives data on clock edge 2
Data Path	-	Logic between launch and capture
Clock Path	-	Clock distribution to both FFs

STA in Design Flow

flowchart TD
    A["RTL Design"] --> B["Synthesis"]
    B --> C["Gate-Level Netlist"]
    C --> D["STA - Pre-Layout"]
    D --> E{"Timing Met?"}
    E -->|No| F["Optimize / Re-synthesize"]
    F --> B
    E -->|Yes| G["Place & Route"]
    G --> H["STA - Post-Layout"]
    H --> I{"Timing Met?"}
    I -->|No| J["ECO / Timing Closure"]
    J --> G
    I -->|Yes| K["Signoff"]
    
    style D fill:#fef3c7,stroke:#f59e0b
    style H fill:#fef3c7,stroke:#f59e0b
    style K fill:#d1fae5,stroke:#10b981

Key Takeaways

• Setup constraint determines maximum operating frequency
• Data must be stable at capture FF before setup time window
• Critical path = longest delay path = frequency limiter
• Positive slack = timing met; Negative slack = violation
• STA runs at synthesis (pre-layout) and after P&R (post-layout)

Next: Hold Time & Clock Skew

Hold time constraints and clock skew add complexity to timing analysis. These will be covered in follow-up posts.