- Setup time constraint is useful for determining maximum Clock frequency given circuit can work reliably.
- Considering combinational logic on Register to Register path, figure given below explains derivation of Clock Period.
Here,
- TFF1 = maximum clock-to-Q delay for FF1.
- TComb = Maximum propagation delay of combinational logic.
- TSetup = Setup time for FF2 (Capture Flip-Flop).
Very important thing to note here is Tc2q delay, which is for Launch Flip-Flop. And TSetup is for Capture Flip-Flop.
Reason being, We need data input to FF2 (Capture FF) stable before Setup time when active edge of clock comes. This data is coming from FF1-Combinational Logic pair. If we ensure that after first clock edge data takes maximum time to reach input of FF2 (Q_C_2), and also signal is stable on or before Setup time. We say that data will be latched to FF2 properly. That is the reason clock time period Tclock should be greater that sum of maximum Delay + Setup time.
TClock ≥ TFF1 + TComb + TSetup
