3. STA Fundamentals - Reset Recovery & Removal Time

In systems with asynchronous reset, the reset signal can be asserted at any time regardless of the clock. However, reset deassertion (release) must follow specific timing requirements to avoid metastability.

Terminology

• Reset Assertion: Applying the reset signal (entering reset state)
• Reset Deassertion: Releasing the reset signal (exiting reset state)

Recovery Time

Reset Recovery Time is the minimum time the reset signal must be stable (deasserted) before the active clock edge.

• Analogous to setup time for data signals
• Reset must not be released during this window before the clock edge

Removal Time

Reset Removal Time is the minimum time the reset signal must remain stable after the active clock edge.

• Analogous to hold time for data signals
• Reset must not be released during this window after the clock edge

Timing Diagram

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gantt
    title Reset Timing Requirements
    dateFormat X
    axisFormat %s
    
    section Clock
    Active Edge :milestone, 50, 0
    
    section Reset
    Recovery Time (before edge) :crit, 30, 50
    Removal Time (after edge) :crit, 50, 70
    Safe Deassertion Zone :done, 0, 30
    Safe Deassertion Zone :done, 70, 100

Comparison with Data Timing

Reset Timing	Data Timing	Description
Recovery Time	Setup Time	Constraint before clock edge
Removal Time	Hold Time	Constraint after clock edge

Best Practice: Use a reset synchronizer to safely deassert asynchronous resets. This ensures the reset release is synchronized to the clock domain, avoiding recovery/removal violations.

This is part 3 of the STA Fundamentals series.