Verilog Code for FIFO with Parameter

//////////////////////////////////////////////
// Module Name: fifo
// Active Low Asynchronous Reset
// Active low read and write enable
// Size of fifo defined by parameter
//////////////////////////////////////////////

module fifo#(parameter DEPTH = 16, WIDTH = 8, ADDR = 5)( 
  input clock, reset, read_n, write_n, 
  input   [WIDTH-1:0] data_in, 
  output reg [WIDTH-1:0]data_out, 
  output  reg full, empty);


 // Define Read and Write pointer
 reg [ADDR-1:0] rd_ptr, wr_ptr;

 integer i;  //Loop constant

 //Define FIFO memory
 reg [WIDTH-1:0] mem [DEPTH-1:0];

 always@(posedge clock or negedge reset)
 begin: data_operation
  if(!reset)
   for(i = 0; i < DEPTH; i=i+1)
    mem[i] <= 0;
  else
  begin 
   if(!write_n && !full)
    mem[wr_ptr[ADDR-1:0]] <= data_in;
   if(!read_n && !empty)
    data_out <= mem[rd_ptr[ADDR-1:0]];
  end
 end //data_operation

 always@(posedge clock or negedge reset)
 begin: rd_wr_addr
  if(!reset)
  begin
   rd_ptr <= 0;
   wr_ptr <= 0;
  end
  else
  begin
   if(!read_n && !empty)
    rd_ptr <= rd_ptr + 1;
   if(!write_n && !full)
    wr_ptr <= wr_ptr + 1;
  end
 end //rd_wr_addr

 always@(rd_ptr or wr_ptr)
 begin: full_empty
  if(rd_ptr == wr_ptr)
   empty = 1;
  else
   empty = 0;
  if((rd_ptr[ADDR] != wr_ptr[ADDR])||(rd_ptr[ADDR-1:0] == wr_plus[ADDR-1:0]))
   full = 1;
  else
   full = 0;
 end

endmodule