Interview Question - Analog Devices

Company: Analog Devices

Question

Analyze the following Verilog code and determine the waveform for signals clk and a.

module stratified_event;
  reg a, clk;

  always
    #10 clk = ~clk;

  always @(posedge clk) begin
    $display($time);
    a <= #15 clk;
  end

  initial begin
    clk = 1'b1;
    a = 1'b0;
    #200 $finish;
  end

endmodule

Analysis

Clock Behavior

• clk starts at 1 (initial block)
• Toggles every 10 time units
• Period = 20 time units

Signal 'a' Behavior

• a starts at 0
• On each posedge clk, samples clk value (always 1)
• Assigns to a after 15 time unit delay (intra-assignment delay)
• Since clk=1 at every posedge, a becomes 1 at t=25 and stays 1

Timing Diagram

Time	Event	clk	a
0	Initial	1	0
10	posedge clk, schedule a<=1 at t=25	0	0
20	clk toggles	1	0
25	a updated	1	1
30	posedge clk	0	1

Key Concept: The #15 is an intra-assignment delay - it samples clk immediately but delays the assignment to a by 15 time units.