1. Verilog RAM - Single Port Async Design

A Single Port RAM has one bidirectional data port that can either read or write. This design uses two control signals: wr_en (write enable) and o_en (output enable). Only one signal should be active at a time.

Features

• Parameterized: Configurable WIDTH, DEPTH, and ADDR
• Asynchronous: No clock required
• Bidirectional data port: Uses tristate for read/write
• Reset: Clears all memory locations to zero

Port Description

Port	Direction	Description
data	inout	Bidirectional data bus [WIDTH-1:0]
addr	input	Address bus [ADDR-1:0]
reset	input	Asynchronous reset (active high)
wr_en	input	Write enable
o_en	input	Output enable (read)

RTL Implementation

// Module: sp_ram.v
// Parameterized Single Port Asynchronous RAM

module sp_ram #(
  parameter WIDTH = 8,
  parameter DEPTH = 16,
  parameter ADDR  = 4
)(
  inout  [WIDTH-1:0] data,
  input  [ADDR-1:0]  addr,
  input              reset,
  input              wr_en,
  input              o_en
);

  // Memory array
  reg [WIDTH-1:0] mem [DEPTH-1:0];
  integer i;

  // Read Operation (active when o_en=1, wr_en=0)
  assign data = (o_en && !wr_en) ? mem[addr] : {WIDTH{1'bz}};

  // Write Operation
  always @(reset, data, addr, wr_en, o_en) begin
    if (reset) begin
      // Clear all memory on reset
      for (i = 0; i < DEPTH; i = i + 1)
        mem[i] = 0;
    end
    else if (wr_en && !o_en) begin
      // Write data to addressed location
      mem[addr] = data;
    end
  end

endmodule

Operation Modes

wr_en	o_en	Operation
0	0	Idle (data = Hi-Z)
0	1	Read from mem[addr]
1	0	Write to mem[addr]
1	1	Invalid (avoid)

Next: Continue to Part 2 - Single Port Testbench