Single Port Asynchronous RAM RTL

• Single Port RAM has only one data port that can either read or written to. For this purpose we need two control signal as "write enable" and "output enable". Only 1 of the 2 signals will be high at a time.
• Testbench for Single Port Asynchronous RAM here.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

///////////////////////////////////////////////// // Module: sp_ram.v // Parameterized Single Port Asynchronous RAM module sp_ram #(parameter WIDTH = 8, DEPTH = 16, ADDR = 4) ( data, addr, reset, wr_en, o_en); //Port Declaration inout [WIDTH-1:0] data; input [ADDR-1:0] addr; input reset; input wr_en, o_en; //Define Memory reg [WIDTH-1:0] mem[DEPTH-1:0]; integer i; //Read Operation assign data = (o_en && (!wr_en))?mem[addr]:'bz; //Write Operation always@(reset, data, addr, wr_en, o_en) begin if(reset) begin for(i = 0; i < DEPTH; i = i + 1) mem[i] = 0; end else if(wr_en && (!o_en)) mem[addr] = data; end endmodule