Resources are always one of the best stuffs to get going into the things. You should go through following books once to achieve complete mastery in VLSI Design/Verification.
Language Reference Manuals
Language Reference Manuals
- IEEE 1076: VHDL Language Reference Manual Download from IEEE
- IEEE 1364-2005: Verilog Hardware Description Language Download from IEEE
- IEEE 1666-2011: SystemC language Download from IEEE
- IEEE 1800-2012: SystemVerilog (SV) Download from IEEE
- SystemVerilog Online Reference Guide from Aldec
- Standard Universal Verification Methodology Download from Accellera
