Reference - Language & Methodology Manuals

A curated collection of Language Reference Manuals, specifications, and resources for VLSI design and verification engineers.

IEEE Standards

Standard	Description	Link
IEEE 1800-2023	SystemVerilog LRM (latest)	IEEE Xplore
IEEE 1800-2017	SystemVerilog LRM	IEEE Xplore
IEEE 1364-2005	Verilog HDL	IEEE Xplore
IEEE 1076-2019	VHDL LRM	IEEE Xplore
IEEE 1666-2023	SystemC LRM	IEEE Xplore
IEEE 1801-2018	UPF (Unified Power Format)	IEEE Xplore

Verification Methodology

Resource	Description	Link
UVM 1.2	Universal Verification Methodology	Accellera
UVM 2017-1.0	IEEE 1800.2 UVM Standard	IEEE Xplore
OVM 2.1.2	Open Verification Methodology (legacy)	Accellera
PSS 2.1	Portable Stimulus Standard	Accellera

ARM AMBA Specifications

Protocol	Version	Link
AMBA AXI	AXI4, AXI5	ARM Developer
AMBA AHB	AHB5, AHB-Lite	ARM Developer
AMBA APB	APB4, APB5	ARM Developer
AMBA CHI	CHI Issue F	ARM Developer
AMBA ACE	ACE, ACE-Lite	ARM Developer

Interface Standards

Standard	Description	Link
PCIe 6.0	PCI Express Base Specification	PCI-SIG
USB4	Universal Serial Bus Specification	USB-IF
MIPI	CSI, DSI, D-PHY, M-PHY	MIPI Alliance
DDR5	JEDEC DDR5 SDRAM	JEDEC
CXL 3.0	Compute Express Link	CXL Consortium

Online References

Resource	Description	Link
ChipVerify	SystemVerilog & UVM tutorials	chipverify.com
Verification Academy	Siemens/Mentor verification resources	verificationacademy.com
ASIC World	Verilog, SystemVerilog tutorials	asic-world.com
Doulos Knowhow	SystemVerilog golden reference	doulos.com
ClueLogic	UVM tutorials & examples	cluelogic.com

Books

Title	Author	Topic
SystemVerilog for Verification	Chris Spear, Greg Tumbush	SV & OOP
A Practical Guide to UVM	Vanessa Cooper	UVM methodology
Writing Testbenches Using SystemVerilog	Janick Bergeron	Verification
Digital Design and Computer Architecture	Harris & Harris	RTL design
The UVM Primer	Ray Salemi	UVM basics

EDA Vendor Documentation

• Synopsys: VCS, Verdi, DVE documentation
• Cadence: Xcelium, SimVision, Jasper
• Siemens EDA: Questa, ModelSim

Quick Reference

Topic	Go-to Resource
SystemVerilog syntax	IEEE 1800-2017 LRM
UVM base classes	UVM 1.2 Class Reference
SVA assertions	IEEE 1800 Chapter 16
Functional coverage	IEEE 1800 Chapter 19
Constrained random	IEEE 1800 Chapter 18
DPI-C	IEEE 1800 Chapter 35