2. Verilog RAM - Single Port Testbench

This testbench verifies the Single Port Asynchronous RAM using Verilog tasks for clean, reusable test operations.

Testbench Features

• Task-based architecture: Modular read/write operations
• Bidirectional data handling: Proper tristate driver for data bus
• Sequential test: Write all locations, then read back

Testbench Implementation

module sp_ram_tb;

  parameter WIDTH = 8;
  parameter ADDR  = 4;
  parameter DEPTH = 16;

  // Signals
  wire [WIDTH-1:0] data;
  reg  [WIDTH-1:0] temp;
  reg              reset, wr_en, o_en;
  reg  [ADDR-1:0]  addr;
  integer i;

  // DUT instantiation
  sp_ram inst(data, addr, reset, wr_en, o_en);

  // Tristate driver for write operations
  assign data = (wr_en && !o_en) ? temp : 'bz;

  // Initialize task
  task init_t;
  begin
    {addr, reset, wr_en, o_en} = 0;
  end
  endtask

  // Delay task (10 time units)
  task delay;
  begin
    #10;
  end
  endtask

  // Reset task
  task reset_t;
  begin
    reset = 1;
    delay;
    reset = 0;
  end
  endtask

  // Read task
  task read_t;
    input [ADDR-1:0] rd_addr;
  begin
    wr_en = 0;
    o_en  = 1;
    addr  = rd_addr;
  end
  endtask

  // Write task
  task write_t;
    input [WIDTH-1:0] data_in;
    input [ADDR-1:0]  wr_addr;
  begin
    o_en  = 0;
    wr_en = 1;
    addr  = wr_addr;
    temp  = data_in;
  end
  endtask

  // Test sequence
  initial begin
    init_t;
    reset_t;

    // Write to all locations (data = 50+i at addr i)
    for (i = 0; i < DEPTH; i = i + 1) begin
      write_t(50 + i, i);
      delay;
    end

    // Read back in reverse order
    for (i = 0; i < DEPTH; i = i + 1) begin
      read_t(DEPTH - 1 - i);
      delay;
    end
  end

endmodule

Test Sequence

1. Initialize: Clear all signals
2. Reset: Clear RAM contents
3. Write Phase: Write values 50-65 to addresses 0-15
4. Read Phase: Read back from addresses 15-0

Expected Results

Address	Written Data	Read Back
0	50 (0x32)	50
1	51 (0x33)	51
...	...	...
15	65 (0x41)	65

Next: Continue to Part 3 - Dual Port Async RAM