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78 | module sp_ram_tb;
parameter WIDTH = 8,
ADDR = 4,
DEPTH = 16;
wire [WIDTH-1:0] data;
reg [WIDTH-1:0] temp;
reg reset, wr_en, o_en;
reg [ADDR-1:0] addr;
integer i;
//Instantiate
sp_ram inst(data, addr, reset, wr_en, o_en);
assign data = (wr_en && (!o_en))?temp:'bz;
//Initialize task
task init_t;
begin
{addr, reset, wr_en, o_en} = 0;
end
endtask
//Delay task
task delay;
begin
#10;
end
endtask
//Reset task
task reset_t;
begin
reset = 1;
delay;
reset = 0;
end
endtask
task read_t;
input [ADDR-1:0] rd_addr;
begin
wr_en = 0;
o_en = 1;
addr = rd_addr;
end
endtask
task write_t;
input [WIDTH-1:0] data_in;
input [ADDR-1:0] wr_addr;
begin
o_en = 0;
wr_en = 1;
addr = wr_addr;
temp = data_in;
end
endtask
initial
begin
init_t;
reset_t;
for(i = 0; i < DEPTH; i = i + 1)
begin
write_t(50+i, i);
delay;
end
for(i = 0; i < DEPTH; i = i + 1)
begin
read_t(DEPTH-1-i);
delay;
end
end
endmodule
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