Verilog Pattern Printing - Power Series | Interview Question Deep Dive

A classic VLSI/Verilog interview question that tests your understanding of loops, the power operator, and output formatting. Let's break it down completely.

The Question

Write Verilog code to display the following pattern:

1
2  4
3  9  27
4  16 64  256
5  25 125 625 3125

Pattern Analysis

Before coding, let's understand the pattern:

Row	Values	Pattern
1	1	11
2	2, 4	21, 22
3	3, 9, 27	31, 32, 33
4	4, 16, 64, 256	41, 42, 43, 44
5	5, 25, 125, 625, 3125	51, 52, 53, 54, 55

Key observation: Row i contains i values, where each value is ij for j = 1 to i.

Key Concepts

1. Power Operator (**)

Verilog supports the power operator:

result = base ** exponent;

// Examples:
2 ** 3  = 8      // 2 cubed
5 ** 2  = 25     // 5 squared
i ** j           // i to the power j

Synthesis Note: The ** operator is synthesizable only when both operands are constants. For variable operands, it's simulation-only.

2. $write vs $display

System Task	Behavior	Use Case
$display	Prints + adds newline	End of line output
$write	Prints without newline	Same-line output

$write("A");     // Output: A (no newline)
$write("B");     // Output: AB (continues on same line)
$display("C");   // Output: ABC\n (adds newline)

Solution

module pattern_power;

  integer i, j;

  initial begin
    $display("Power Pattern:");
    $display("-------------");
    
    for (i = 1; i <= 5; i = i + 1) begin
      for (j = 1; j <= i; j = j + 1) begin
        $write("%5d ", i**j);  // %5d for aligned columns
      end
      $display();  // Newline after each row
    end
  end

endmodule

Output

Power Pattern:
-------------
    1 
    2     4 
    3     9    27 
    4    16    64   256 
    5    25   125   625  3125 

Code Walkthrough

flowchart TD
    A["Start: i = 1"] --> B{"i <= 5?"}
    B -->|Yes| C["j = 1"]
    C --> D{"j <= i?"}
    D -->|Yes| E["Print i^j"]
    E --> F["j++"]
    F --> D
    D -->|No| G["Print newline"]
    G --> H["i++"]
    H --> B
    B -->|No| I["End"]
    
    style A fill:#d1fae5,stroke:#10b981
    style I fill:#fee2e2,stroke:#ef4444
    style E fill:#dbeafe,stroke:#3b82f6

Alternative Approaches

Approach 2: Using Multiplication (Synthesizable)

Avoid the power operator for synthesis:

module pattern_multiply;

  integer i, j, power;

  initial begin
    for (i = 1; i <= 5; i = i + 1) begin
      power = 1;  // Reset for each row
      for (j = 1; j <= i; j = j + 1) begin
        power = power * i;  // Multiply instead of power
        $write("%5d ", power);
      end
      $display();
    end
  end

endmodule

Approach 3: Using Arrays

module pattern_array;

  integer i, j;
  integer powers [1:5];  // Store computed powers

  initial begin
    for (i = 1; i <= 5; i = i + 1) begin
      for (j = 1; j <= i; j = j + 1) begin
        powers[j] = i ** j;
        $write("%5d ", powers[j]);
      end
      $display();
    end
  end

endmodule

Common Mistakes

Mistake	Problem	Fix
Using $display in inner loop	Each number on new line	Use $write, then $display() after inner loop
Wrong loop bounds	j < i instead of j <= i	Check pattern requirements carefully
Missing initialization	Uninitialized i or j	Declare as integer (auto-initialized to 0)
Overflow for large values	Integer overflow	Use appropriate data types or limit range

Follow-up Questions

Interviewers often extend this question:

Q1: Print the pattern in reverse

// Output:
// 5  25 125 625 3125
// 4  16 64  256
// 3  9  27
// 2  4
// 1

for (i = 5; i >= 1; i = i - 1) begin
  // ... same inner loop
end

Q2: Make it parameterizable

module pattern_param #(parameter N = 5);
  integer i, j;
  
  initial begin
    for (i = 1; i <= N; i = i + 1) begin
      for (j = 1; j <= i; j = j + 1)
        $write("%5d ", i**j);
      $display();
    end
  end
endmodule

Q3: Print as a right-aligned triangle

// Add leading spaces
for (i = 1; i <= 5; i = i + 1) begin
  // Print leading spaces
  for (j = i; j < 5; j = j + 1)
    $write("      ");  // 6 spaces per column
  // Print values
  for (j = 1; j <= i; j = j + 1)
    $write("%5d ", i**j);
  $display();
end

Interview Tips

• Analyze first: Always explain the pattern before coding
• Know limitations: Mention that ** isn't synthesizable with variables
• Show alternatives: Offering multiple approaches demonstrates depth
• Consider edge cases: What if N is 0? Negative? Very large?
• Format output: Using %5d shows attention to detail

Related Questions

• Print Floyd's Triangle
• Print Pascal's Triangle in Verilog
• Generate Fibonacci sequence
• Print multiplication table

Key Takeaways

• ** is the power operator in Verilog (simulation only for variables)
• Use $write for same-line output, $display for newline
• Nested loops: outer controls rows, inner controls columns
• For synthesis, use multiplication instead of power operator