Q.2 Write Verilog code to display following pattern.
1
2 4
3 9 27
4 16 64 256
5 25 125 625 3125
Code:
Here, ** is a power operator. It can be Synthesized only if both the operands are constant.
1
2 4
3 9 27
4 16 64 256
5 25 125 625 3125
Code:
Here, ** is a power operator. It can be Synthesized only if both the operands are constant.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | module pattern; integer i,j; initial begin for(i = 1; i < 6; i = i + 1) begin for(j = 1; j <= i; j = j + 1) begin $write("%d", i**j); end $display(); end end endmodule |
