UPF & Low Power Verification
UPF & Low Power Verification
Master power-aware verification using UPF (IEEE 1801) for mobile, IoT, and power-sensitive designs.
Why Low Power Verification?
Modern SoCs have dozens of power domains, multiple voltage levels, and complex power state machines. Bugs in low power implementation cause silicon failures that are expensive to fix.
- Power domains require proper isolation and level shifting
- Retention must save/restore state correctly
- Sequencing errors can corrupt data or cause shorts
This guide covers UPF from basics to verification strategies.
Module 1: Foundations
Core low power concepts before diving into UPF.
Why Low Power Matters
Mobile/IoT constraints, dynamic vs static power, thermal limits, and power budgets.
Power Domains
Partitioning design by power requirements, always-on vs switchable domains.
Voltage Levels
Multi-voltage design, voltage islands, and voltage scaling techniques.
Power States
Active, standby, sleep, off states and transition management.
Module 2: UPF Basics (IEEE 1801)
Learn the Unified Power Format specification.
UPF Introduction
What is UPF, CPF vs UPF history, file structure and design flow.
Supply Networks
create_supply_net, create_supply_port, supply states (ON, OFF, PARTIAL_ON).
Power Domains
create_power_domain, scope, elements, nested domains, and default domain.
Power States
add_power_state, Power State Table (PST), legal/illegal state transitions.
Module 3: Low Power Cells
Special cells that enable power management.
Power Switches
MTCMOS switches, header vs footer cells, set_power_switch, daisy-chaining.
Isolation Cells
Clamp high/low, latch isolation, set_isolation, -applies_to, -clamp_value.
Level Shifters
HL/LH shifters, enable-based shifters, set_level_shifter, -location.
Retention Registers
Save/restore signals, balloon latches, set_retention configuration.
Always-On Logic
AON requirements, AON buffers, feed-through signals, routing.
Module 4: Verification Strategies
How to verify low power designs effectively.
Power-Aware Simulation
Corruption semantics, X-propagation, PA-SIM vs standard simulation.
Isolation Verification
Checking proper clamping, isolation before power-off, assertions.
Retention Verification
Save before power-off, restore after power-on, data integrity checks.
Power Sequencing
Power-up/down sequences, dependency ordering, sequence verification.
Coverage Models
Power state coverage, transition coverage, scenario coverage.
Module 5: Practical DV
Real-world verification patterns and debugging.
UVM & Low Power
Power-aware testbench architecture, power controller component, sequences.
Common Bugs
Missing isolation, wrong level shifter, retention failures, sequencing errors.
Debug Techniques
Power-aware waveforms, UPF debug reports, supply network visualization.
Quick Reference
Handy references for daily use.
This page is regularly updated with new content. Have a topic suggestion? Leave a comment on any post!