PCIe Layer Visualizer - Interactive User Guide

Interactive tool for understanding PCIe packet flow through the protocol stack. Step through transactions layer-by-layer and observe how TLPs traverse from Root Complex to Endpoint.

Launch PCIe Layer Visualizer

Quick Start

1. Click + MRd to queue a Memory Read transaction
2. Click Step to advance through each protocol step
3. Watch the packet traverse TL → DLL → PHY → Link → PHY → DLL → TL
4. Observe ACK DLLP return to complete the handshake

Interface Overview

Component	Purpose
Config Panel	Set link speed (Gen1-5), width (x1-16), retry buffer size, flow control credits
Controls	Queue transactions (MRd/MWr/CfgRd), Play/Step/Reset, inject errors
Layer Diagram	RC and EP stacks with active layer highlighting and function tag indicators
Status Bar	Sequence numbers, timer, buffer slots, credits, statistics
Packet View	Current packet structure with field breakdown and bit widths
Trace Log	Timestamped protocol events in terminal style

15-Step Packet Flow

Each transaction executes a complete round-trip:

TLP Transmission (Steps 1-10)

#	Location	Action
1	RC TL	Create TLP (Type, Length, Tag)
2	RC DLL	Add 12-bit Sequence Number
3	RC DLL	Calculate 32-bit LCRC
4	RC DLL	Store in Retry Buffer, start timer
5	RC PHY	8b/10b encode + scramble
6	Link	Transmit TLP
7	EP PHY	Descramble + 8b/10b decode
8	EP DLL	Verify LCRC
9	EP DLL	Check Sequence Number
10	EP TL	Deliver TLP

ACK Response (Steps 11-15)

#	Location	Action
11	EP DLL	Generate ACK DLLP
12	EP PHY	Encode ACK
13	Link	Transmit ACK
14	RC PHY	Decode ACK
15	RC DLL	Free buffer, stop timer

Error Injection

Scenario	How to Test	What Happens
LCRC Error	Click LCRC Error → queue TLP → step	EP detects bad CRC → sends NAK → RC replays from buffer
ACK Timeout	Click Drop ACK → queue TLP → step	ACK lost → timer expires → RC triggers replay
Recovery	Exceed max replay count	Link enters RECOVERY state

Key Counters

Counter	Description
TX_SEQ	Next sequence number to assign (0-4095)
ACKD_SEQ	Last acknowledged sequence number
NEXT_RCV_SEQ	Expected sequence number at receiver
Retry Buffer	Amber=pending, Purple=replaying, Green=ACKed
Flow Credits	PH/PD (posted), NPH/NPD (non-posted), CplH/CplD (completion)

Current Features

• Full TLP + ACK + Completion visualization with layer-by-layer traversal
• Function tag highlighting (Seq Number, LCRC, ACK/NAK, 8b/10b light up during execution)
• Configurable link (Gen1-5, x1-16) and protocol parameters
• LCRC error injection and NAK-triggered replay
• ACK drop with replay timer timeout
• Transaction types: MRd, MWr, CfgRd
• Real-time trace logging
• Completion Flow - CplD returns for non-posted requests (MRd/CfgRd), with ACK back to EP
• Flow Control - UpdateFC DLLP visualization, credit consumption and restoration

Future Enhancements

Protocol Features

• Multiple Outstanding - Parallel TLPs in flight with tag management
• Ordering Rules - Posted/Non-posted/Completion ordering demonstration
• All TLP Types - IO, Message, AtomicOp transactions

Error & Recovery

• Sequence Mismatch - Out-of-order packet detection
• Credit Exhaustion - Receiver overflow scenario
• ECRC Errors - End-to-end CRC (optional TLP field)
• Malformed TLP - Invalid packet handling and error reporting
• Poisoned TLP - Data corruption signaling

Advanced Protocol

• LTSSM Visualization - Link Training states (Detect → Polling → Config → L0)
• Power Management - L0s/L1/L2 state transitions and exit latency
• Switch Topology - Multi-device routing with upstream/downstream ports
• MSI/MSI-X - Interrupt signaling mechanism
• AER - Advanced Error Reporting with error classification
• SR-IOV - Virtual function visualization
• IDE - Integrity and Data Encryption (PCIe 6.0)

DV Engineer Tools

• Scenario Library - Pre-built test scenarios (normal, error, corner cases)
• Coverage Tracking - Protocol scenario coverage metrics
• Assertion View - SVA-style protocol assertions with pass/fail indicators
• Generate Sequences - Export scenarios as SystemVerilog/UVM sequences
• Import Traces - Load real PCIe analyzer captures for visualization
• Compare Mode - Side-by-side expected vs actual behavior

Analysis & Export

• Bandwidth Calculator - Effective throughput based on config and overhead
• Latency Estimation - Transaction latency breakdown by layer
• Timeline View - Gantt-style transaction timeline
• Waveform Export - Generate timing diagrams (WaveDrom/VCD)
• Packet Hex View - Raw byte-level packet visualization
• PDF Report - Export session summary for documentation

Educational

• Guided Tutorials - Step-by-step lessons for specific concepts
• Quiz Mode - Test understanding with interactive questions
• Spec References - Links to relevant PCIe specification sections
• Annotations - Add notes to specific steps for teaching

Tips for DV Engineers

1. ACK/NAK Timing - Use "Drop ACK" to understand replay timer protection
2. Error Recovery - Inject LCRC errors to trace the NAK → Replay flow
3. Sequence Tracking - Watch TX_SEQ increment and ACKD_SEQ update on ACK
4. Buffer Management - Observe TLPs held in retry buffer until acknowledged
5. Configuration Impact - Vary buffer sizes and replay counts to understand tradeoffs

Last updated: January 2026