P5. SystemC Tutorial - AND Gate with Testbench

The AND gate is structurally identical to the OR gate from Part 4 — the only change is the operator. So this final part of the series spends most of its time on what we've actually built up across Parts 1–5, and where to take it from here.

Implementation

#include "systemc.h"

// AND Gate Module
SC_MODULE(and_gate) {
  sc_in<bool>  a, b;
  sc_out<bool> c;

  void and_gate_p() {
    c.write(a.read() & b.read());
  }

  SC_CTOR(and_gate) {
    SC_METHOD(and_gate_p);
    sensitive << a << b;
  }
};

int sc_main(int argc, char* argv[]) {
  sc_signal<bool> a, b, c;

  and_gate and1("and_gate_and1");
  and1.a(a);
  and1.b(b);
  and1.c(c);

  sc_trace_file* tf = sc_create_vcd_trace_file("and_gate");
  tf->set_time_unit(1, SC_NS);
  sc_trace(tf, a, "a");
  sc_trace(tf, b, "b");
  sc_trace(tf, c, "c");

  // Walk the truth table
  a = 0; b = 0; sc_start(1.0, SC_NS);
  a = 0; b = 1; sc_start(1.0, SC_NS);
  a = 1; b = 0; sc_start(1.0, SC_NS);
  a = 1; b = 1; sc_start(1.0, SC_NS);

  sc_stop();
  sc_close_vcd_trace_file(tf);
  cout << "Finished at time " << sc_time_stamp() << endl;
  return 0;
}

Truth Table and Waveform

A	B	C (A&B)
0	0	0
0	1	0
1	0	0
1	1	1

What you've built across Parts 1–5

Stepping back, here's the toolkit you now have:

SystemC concept	Where it appeared	Verilog/SV analogue	UVM analogue
SC_MODULE	P3 — first inverter	module ... endmodule	uvm_component hierarchy
sc_in / sc_out	P3 — port declarations	input / output	Interface ports on a driver
sc_signal	P3 — connecting modules	wire / logic	Interface signals
SC_METHOD + sensitivity	P3 — combinational behavior	always @*	Monitor's signal-watcher
Truth-table testbench	P4, P5 — directed stimulus	initial stimulus	uvm_sequence with directed items
sc_trace / VCD	P3, P4, P5 — waveform dump	$dumpvars	Standard sim infrastructure
sc_assert	P4 — self-checking	assert	uvm_scoreboard base pattern

Every concept in the right two columns is a generalization of what's in the left two. SystemC isn't a smaller language than SystemVerilog — it's a different abstraction level. You'll meet the same patterns in TLM-2.0 with much richer payloads.

Where to go from here

1. Add state. Try a 4-bit counter using SC_METHOD sensitive to a clock. You'll meet sc_event, posedge sensitivity, and the question of whether to use a SC_THREAD instead.
2. Add channels. Replace point-to-point sc_signal with sc_fifo for producer/consumer scenarios. This is one step away from TLM-2.0.
3. Build a TLM-2.0 model. The standard interface for transaction-level modeling. The Capstone 2 post walks through a complete RV32I CPU model using these building blocks.
4. Co-simulate with RTL. Most production flows wrap a SystemC reference model around an RTL DUT and run them in lockstep. SystemVerilog DPI is the bridge.

References

• systemc.org — official documentation and downloads
• IEEE 1666-2011 LRM — the authoritative spec
• D. C. Black et al., SystemC: From the Ground Up — best book for systematic learning
• Accellera SystemC Forum — for tricky kernel/scheduling questions

That wraps up the SystemC tutorial series. The combinational gates are deliberately small — they're the smallest possible vehicle for the patterns you'll use everywhere else.

← Part 4: OR Gate Part 5 of 5