Basic Gates using SystemC - AND Gate and Testbench

//Include SystemC library definitions
#include "systemc.h"

// AND Gate Module
SC_MODULE(and_gate){
 sc_in a, b; // Input of type bool
 sc_out c;  // Output of type bool

 // Process(Funtionality of AND)
 void and_gate_p(){
  c.write(a.read() & b.read());
 }

 // Constructor for AND Gate module
 SC_CTOR(and_gate){
  SC_METHOD(and_gate_p);
  // Process sensitivity
  sensitive << a << b;
 }
};

// AND Gate testbench
int sc_main(int argc, char* argv[]){

 // testbench signals
 sc_signal a, b, c;

 // Trace file pointer to store waveforms in VCD
 sc_trace_file *tf;

 // Module instantiation and name based connection
 and_gate and1("and_gate_and1");
 and1.a(a);
 and1.b(b);
 and1.c(c);

 // Trace file name and timescale unit
 tf = sc_create_vcd_trace_file("and_gate");
 tf->set_time_unit(1, SC_NS);

 // Trace file signals
 sc_trace(tf, a, "a");
 sc_trace(tf, b, "b");
 sc_trace(tf, c, "c");


 a = 0;
 b = 0;
 sc_start(1.0, SC_NS);

 a = 0;
 b = 1;
 sc_start(1.0, SC_NS);

 a = 1;
 b = 0;
 sc_start(1.0, SC_NS);

 a = 1;
 b = 1;
 sc_start(1.0, SC_NS);

 sc_stop();

 // Close trace file
 sc_close_vcd_trace_file(tf);

 // Display end simulation time
 cout << "Finished at time " << sc_time_stamp() << endl;

 return 0;
}