SystemVerilog Interface - Counter DUT

• Interface module takes clock as input
• And Clocking Blocks define directions in each BFM (Similer to Driver/ Monitor in UVM), Refer Chrish Spear book for more on Clocking Block
• Modports makes use of clocking block, So three modports needed to be created for each BFM (Write BFM, Write Monitor, Read Monitor)
• Counter Interface Filename is counter_if.sv

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interface counter_if(input logic clk); logic rst, updown, load; logic [3:0] data; logic [3:0] data_out; clocking wr_cb@(posedge clk); output load, updown, rst; output data; endclocking clocking wrmon_cb@(posedge clk); input data; input load, rst, updown; endclocking clocking rdmon_cb@(posedge clk); input data_out; endclocking modport WR_BFM(clocking wr_cb); modport WR_MON(clocking wrmon_cb); modport RD_MON(clocking rdmon_cb); endinterface: counter_if