SV Testbench is created for given Counter DUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 | module counter(clk, rst, data, updown, load, data_out); input clk, rst, load; input updown; input [3:0] data; output reg [3:0] data_out; always@(posedge clk) begin if(rst) data_out <= 4'b0; else if(load) data_out <= data; else data_out <= ((updown)?(data_out + 1'b1):(data_out -1'b1)); end endmodule |
