3. SystemC Tutorial - Inverter Gate

This example demonstrates a basic Inverter (NOT gate) implementation in SystemC with a testbench.

Key Concepts

  • SC_MODULE - Defines a SystemC module
  • sc_in<bool> / sc_out<bool> - Input and output ports
  • SC_METHOD - Process that runs when sensitive signals change
  • sc_trace - Records signals to VCD waveform file

Implementation

#include "systemc.h"

// NOT Gate Module
SC_MODULE(not_gate) {
  sc_in<bool> aIn;   // Input port
  sc_out<bool> aOut; // Output port

  // Inverter functionality
  void not_gate_p() {
    aOut = !aIn;
  }

  // Constructor
  SC_CTOR(not_gate) {
    SC_METHOD(not_gate_p);
    sensitive << aIn;  // Trigger on input change
  }
};

// Testbench
int sc_main(int argc, char* argv[]) {
  // Signals
  sc_signal<bool> aOut;
  sc_clock aIn("aIn", 5, SC_NS);  // 5ns clock period

  // VCD trace file
  sc_trace_file *tf;

  // Instantiate and connect
  not_gate n1("not_gate_n1");
  n1.aIn(aIn);
  n1.aOut(aOut);

  // Setup tracing
  tf = sc_create_vcd_trace_file("not_gate");
  tf->set_time_unit(1, SC_NS);
  sc_trace(tf, aIn, "aIn");
  sc_trace(tf, aOut, "aOut");

  // Run simulation
  sc_start(100, SC_NS);

  // Cleanup
  sc_close_vcd_trace_file(tf);
  cout << "Finished at time " << sc_time_stamp() << endl;

  return 0;
}

Output

The simulation generates a VCD file (not_gate.vcd) showing the inverted output waveform.

Next: Continue to Part 4 - OR Gate

Author
Mayur Kubavat
VLSI Design and Verification Engineer sharing knowledge about SystemVerilog, UVM, and hardware verification methodologies.

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