Top Module for Counter DUT
- Test file consists list of tests needed to run on SystemVerilog Environment.
- Interface provides communication between DUT and BFM Transactors.
- DUT is 4-bit loadable up-down counter with Synchronous Reset signal.
- Assertion contains temporal checks for counter DUT protocol.
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| `include "test.sv"
module top;
reg clk;
counter_if intf(clk);
counter DUV( .clk(clk),
.rst(intf.rst),
.load(intf.load),
.updown(intf.updown),
.data(intf.data),
.data_out(intf.data_out));
bind DUV counter_assertion C_A( .clk(clk),
.rst(intf.rst),
.load(intf.load),
.updown(intf.updown),
.data(intf.data),
.count(intf.data_out));
test test_h;
initial
begin
test_h = new(intf, intf, intf);
test_h.build_and_run();
end
initial
begin
clk = 0;
forever #10 clk = ~clk;
end
endmodule: top
|
